Semiconductor ROM is a type of solid state memory that is fabricated with desired data permanently stored in it. The “on” or “off” state of each memory cell is set by programming the memory. Each memory cell is capable of storing a binary bit of data, representing either a logic state of “0” or “1” depending on whether the path of a bit line to ground (VSS) of the memory cell is electrically connected or electrically isolated.
Designers prefer simple schemes like single end circuits (e.g., inverters) to detect the data state of these memory cells. For example, if the bit line connected to a ROM cell has significant voltage drop (to a lower voltage state) during a read cycle, this condition can represent a logic value of “1.” If the bit line of the ROM cell remains unchanged (e.g., at a higher voltage), this condition represents a logical value of “0.” The definition of “0” and “1” can be switched. Typically the connection is sensed by detecting a significant pull-down on the bit-line, which often involves waiting a significant period for transistor transition and/or settling times to elapse. For high speed ROM design, U.S. Pat. No. 6,850,427 uses differential sensing with a single transistor element to create a differential signal on two bit-lines. However, the single transistor cell structure provides shrinkage challenges for future technology generations, like OD minimum area (small island) induced lithography process margin and integration problems. Conventional ROM cell designs have an OD length that extends only across a range of two transistors. This layout results in problems relating to lithography printing, pattern lifting, line-end shortening, contact landing and CD uniformity. As cell sizes continue to shrink, the lithography process margins shrink. The lithography process margin impacts the patterning and active region CDU, which impacts read current and Vt matching stability. This is due to the tight space allotted for the small island (minimum area) cell environment described above. The conventional layout also has issues with the landing margin when the contact is positioned at a line-end.
As mentioned above, the cell state is detected by a sense amplifier that translates the “on” or “off” state into a logic “1” or a logic “0”, respectively, or vice versa. The sense amplifier can detect either voltage or current. A difference, either voltage or current, between the cell transistor's “on” and “off” states should be as large as possible, so that the sense amplifier can quickly and correctly detect the state. In a traditional ROM cell, the difference is largely determined by the cell transistor's channel width and channel length. As the processing technology enters the nanometer era, the cell transistor's channel width and channel length exhibit a significant sensitivity to its layout environments, including the poly (or gate) spacing effect (PSE) and the shallow-trench-isolation (STI) stress effect (LOD) and strain effect. These effects may significantly affect the channel width and channel length, and hence lower the cell transistor's sensing margin.
Differences in source/drain (S/D) area opening, as determined by the gate space, will result in a different junction distribution across the memory array, and therefore impact performance characteristics like device drive current, threshold voltage, and junction leakage. This is known as the aforementioned poly or gate spacing effect (PSE). This effect is also a function of the poly space rule or OD extension rule. Having a similar gate environment across a full cell array is important in cell design.
Recently, the shallow trench isolation (STI) stress effect has been observed. The STI induces a compressive or tensile stress on the transistor S/D regions. If the extension rule of the S/D regions-to-gate is too small, the stress induced Ion and Vt shift will vary dramatically when compared to longer extension rules. As such, the transistor's performance will change from layout differences or lithographic misalign induced OD extension imbalances. This results in poor matching performance on cell devices and wide spreads in chip speed. This effect also impacts yield.
Increasing transistor size (cell size) or decreasing the memory's operation speed can compensate for these layout environmental effects, but these modifications impact product cost and/or performance.
There remains a need for an improved ROM cell structure with improved mismatch amongst ROM cells and increased performance without substantially increasing the size or decreasing the speed of the ROM array.